The present invention relates to a reconfigurable integrated circuit such as an FPGA (Field-programmable gate array).
FPGAs are increasing their importance rapidly with growing needs to reduce the NRE cost and the design turnaround time resulting from the miniaturization of the semiconductor integrated circuit technology.
FIG. 1 shows a general view of a typical FPGA. 101 is a GSM (Global switch matrix), 102 is an LSM (local switch matrix), and 103 is an LE (Logic Element), and an FPGA is configured basically by arranging identical tiles 104 including these elements. In each of the tiles, there are a plurality of LEs, which can be mutually connected by the LSM. Furthermore, each of the LEs can be connected to the LEs in each tile through the LSM and the GSM. The GSMs are connected to each other by interconnections 105 and 106 arranged in a grid pattern.
As shown in FIG. 2, the LE is typically comprising a programmable logic element (201) such as an LUT (Look Up Table), a memory element (202) such as a DFF (D-Flip Flop), and a multiplexer (203) to control signal paths between them.
FIG. 3 shows a basic circuitry of the GSM and the LSM. The inside of the GSM and the LSM is comprised of a plurality of interconnection switches (multiplexer) for making each input of a switch matrix correspond to each output thereof.
FIG. 4 shows a typical circuitry of an LUT, and the inside thereof is comprised of pass transistors connected in a tree shape and an SRAM (302) connected to the leaf node thereof. Inputs (301) of an LUT is connected to the gate of the pass transistor tree, and each SRAM value corresponding to any combinations of input signals is selected and output to an output 303. Furthermore, 304 is a pull up PMOS to recover a decrease of the signal level due to NMOS pass transistors.
Although FPGAs are one of the integrated circuits capable of receiving the greatest benefits from the miniaturization of the semiconductor integrated circuit technology because of their regular fabric, the increasing leakage current resulting from the miniaturization of the integrated circuit technology has become a problem.
Once reconfigurable integrated circuits such as FPGAs are given functions, a large number of circuit resources thereon are unused, which increases the leakage current. For example, interconnection switches make up a large percentage (80 to 90%) of transistors in FPGAs, however, more than 90% of the interconnection switches are unused during the operation of FPGAs [Non-Patent Document 1]. The leakage current in the unused interconnection switches is extremely large. In order to solve this problem, methods for reducing leakage current in FPGAs by shutting down a power source of an output buffer of unused interconnection switches have been proposed in recent years [Patent Document 1, Non-Patent Document 2, 3, 4].
On the other hand, leakage current in SRAMs for controlling interconnection switches of FPGAs is also large, which makes up 40% of the total leakage current when no countermeasure is taken [Non-Patent Document 7]. The Non-Patent Document 7 discloses that leakage current in SRAM cells can be reduced dramatically by increasing the thickness of gate oxide films of transistors of SRAM cells. This method is applicable because SRAMs of FPGAs do not require high-speed reading and writing.
However, dropping supply voltages or increasing threshold voltages of SRAMs is difficult due to the reduction in the operation margin of SRAM cells resulting from process variation [Refer to Non-Patent Document 5]. Therefore, leakage current in SRAMs will be larger than that in other circuit resources. Furthermore, since the method for increasing the thickness of a gate oxide film increases not only leakage current due to DIBL but also process variation [Non-Patent Document 6], it is not practical to use this method. Thus reducing leakage current in SRAMs is very important in reduction of power consumption in FPGAs.
[Patent Document 1] U.S. Pat. No. 6,914,449
[Non-Patent Document 1] S. Srinivasan et al., “Leakage Control in FPGA Routing Fabric”, Proc. ASP-DAC '05, pp. 661-664.
[Non-Patent Document 2] J. Anderson et al., “Low-power programmable routing circuitry for FPGAs”, Proc. ICCAD '04, pp. 602-609.
[Non-Patent Document 3] A. Rahman et al., “Determination of Power Gating Granularity for FPGA Fabric”, Proc. CICC '06, pp. 9-12.
[Non-Patent Document 4] Y. Lin et al., “Power Modeling and Architecture Evaluation for FPGA with Novel Circuits for Vdd Programmability,” Proc. FPGA '05, pp. 199-207.
[Non-Patent Document 5] E. Morifuji, “Supply and Threshold-Voltage Trends for Scaled Logic and SRAM MOSFETs”, IEEE Trans. Electron Devices, Vol. 53, No. 6, pp. 1427-1432, 2005.
[Non-Patent Document 6] A. Asenov, “Simulation of Intrinsic Parameter Fluctuations in Decananometer and Nanometer-Scale MOSFETs”, IEEE Trans. Electron Devices, Vol. 50, No. 9, pp. 1837-1852, 2003.
[Non-Patent Document 7] T. Tuan, “A 90 nm Low-Power FPGA for Battery-Powered Applications,” Proc. FPGA '06, pp. 3-11.
In the reconfigurable integrated circuits such as FPGAs, leakage current in SRAMs increases relatively with progress in miniaturization of the semiconductor integrated circuit technologies. The purpose of the present invention is to realize reduction of power consumption in reconfigurable integrated circuits such as FPGAs by reducing leakage current in SRAMs.